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Preliminary GS816272CC-xxxV
209-Bump BGA Commercial Temp Industrial Temp Features
* FT pin for user-configurable flow through or pipeline operation * Single/Dual Cycle Deselect selectable * IEEE 1149.1 JTAG-compatible Boundary Scan * ZQ mode pin for user-selectable high/low output drive
256K x 72 18Mb S/DCD Sync Burst SRAMs
Flow Through/Pipeline Reads
250 MHz-150 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O
* 1.8 V or 2.5 V core power supply
The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
* 1.8 V or 2.5 V I/O supply
* LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to SCD x18/x36 Interleaved Pipeline mode * Byte Write (BW) and/or Global Write (GW) operation * Internal self-timed write cycle * Automatic power-down for portable applications * JEDEC-standard 209-bump BGA package * RoHS-compliant 209-bump BGA package available
SCD and DCD Pipelined Reads
The GS816272CC-xxxV is an SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input.
Functional Description
Applications
The GS816272CC-xxxV is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
FLXDriveTM
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Controls
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS816272CC-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V or 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible.
Parameter Synopsis
-250 Pipeline 3-1-1-1 Flow Through 2-1-1-1
tKQ tCycle Curr tKQ tCycle Curr 3.0 4.0 425 5.5 5.5 315
-200
3.0 5.0 345 6.5 6.5 275
-150
3.8 6.7 270 7.5 7.5 250
Unit
ns ns mA ns ns mA
Rev: 1.02a 6/2006
1/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
GS816272CC-xxxV Pad Out--209-Bump BGA--Top View (Package C)
1 A B C D E F G H J K L M N P R T U V W Rev 10 DQG DQG DQG DQG DQPG DQC DQC DQC DQC NC DQH DQH DQH DQH DQPD DQD DQD DQD DQD 2 DQG DQG DQG DQG DQPC DQC DQC DQC DQC NC DQH DQH DQH DQH DQPH DQD DQD DQD DQD 3 A BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 ADSP NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT MCL SCD ZZ VDD LBO A A1 A0 7 ADV A NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 8 E3 BB BE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A BF BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQB DQB DQB DQB DQPF DQF DQF DQF DQF NC DQA DQA DQA DQA DQPA DQE DQE DQE DQE 11 DQB DQB DQB DQB DQPB DQF DQF DQF DQF NC DQA DQA DQA DQA DQPE DQE DQE DQE DQE
11 x 19 Bump BGA--14 x 22 mm2 Body--1 mm Bump Pitch
Rev: 1.02a 6/2006
2/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
GS816272CC-xxxV BGA Pin Description Symbol
A0, A1 A DQA DQB DQC DQD DQE DQF DQG DQH BA, BB, BC,BD, BE, BF, BG,BH NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO SCD MCH MCL BW ZQ TMS TDI TDO TCK VDD VSS VDDQ I I I I O I I I I
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs. Address Inputs
I/O
Data Input and Output pins
I -- I I I I I I I I I I I I
Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Global Write Enable--Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control Must Connect High Must Connect Low Byte Enable; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
Rev: 1.02a 6/2006
3/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
GS816272CC-xxxV Block Diagram
Register
A0-An
D
Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1
A
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q 36 D 36
Register
D BB
Q 4
Register
D BC
Q Q
Register
D
Register
Q
Register
D
D BD
Q
Register
D
Q
36 36
Register
E1 E3 E2
D
Q
36
Register
D
Q
FT G Power Down Control
36
ZZ
0
DQx1-DQx9
Note: Only x36 version shown for simplicity.
Rev: 1.02a 6/2006
4/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control Single/Dual Cycle Deselect Control FLXDrive Output Impedance Control
Pin Name
LBO FT ZZ SCD ZQ
State
L H L H or NC L or NC H L H or NC L H or NC
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Low Drive (High Impedance)
Note: There are pull-up devices on the ZQ, and SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.02a 6/2006
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(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Byte Write Truth Table Function
Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes
GW
H H H H H H H L
BW
H L L L L L L X
BA
X H L H H H L X
BB
X H H L H H L X
BC
X H H H L H L X
BD
X H H H H L L X
Notes
1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4
Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x36 version.
Rev: 1.02a 6/2006
6/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Synchronous Truth Table Operation
Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
X R R W CR CR CW CW
E1
H L L L X H X H X H X H
E2
X F F T T T X X X X X X
ADSP
X L H H H X H X H X H X
ADSC
L X L L H H H H H H H H
ADV
X X X X L L L L H H H H
W3
X X F T F F T T F F T T
DQ4
High-Z Q Q D Q Q D D Q Q D D
Notes: 1. X = Don't Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.02a 6/2006
7/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Simplified State Diagram
X
Deselect W W Simple Synchronous Operation R R
X CW
First Write
R CR
First Read
X CR
Simple Burst Synchronous Operation
W R X Burst Write CR CW
R
Burst Read
X
CR
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low.
Rev: 1.02a 6/2006
8/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Simplified State Diagram with G
X
Deselect W W X W CW R R
First Write
R CR
First Read
X CR
CW
W X Burst Write R CR W CW
R X
Burst Read
CW
CR
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time.
Rev: 1.02a 6/2006
9/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage on VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 4.6 -0.5 to VDD -0.5 to VDDQ +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V mA mA W
oC oC
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Power Supply Voltage Ranges (1.8 V/2.5 V Version) Parameter
1.8 V Supply Voltage 2.5 V Supply Voltage 1.8 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage
Symbol
VDD1 VDD2 VDDQ1 VDDQ2
Min.
1.7 2.3 1.7 2.3
Typ.
1.8 2.5 1.8 2.5
Max.
2.0 2.7 VDD VDD
Unit
V V V V
Notes
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.02a 6/2006
10/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
VDDQ2 & VDDQ1 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage
Symbol
VIH VIL
Min.
0.6*VDD -0.3
Typ.
-- --
Max.
VDD + 0.3 0.3*VDD
Unit
V V
Notes
1 1
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
TA TA
Min.
0 -40
Typ.
25 25
Max.
70 85
Unit
C C
Notes
2 2
Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be -2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKC VDD + 2.0 V
VSS 50% VSS - 2.0 V 20% tKC
50% VDD
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
Rev: 1.02a 6/2006
11/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1 VDDQ/2
* Distributed Test Jig Capacitance
Figure 1
Output Load 1 DQ 50 30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) FT, SCD, ZQ, ZZ Input Current Output Leakage Current
Symbol
IIL IIN IOL
Test Conditions
VIN = 0 to VDD VDD VIN 0 V Output Disable, VOUT = 0 to VDD
Min
-1 uA -100 uA -1 uA
Max
1 uA 100 uA 1 uA
DC Output Characteristics (1.8 V/2.5 V Version) Parameter
1.8 V Output High Voltage 2.5 V Output High Voltage 1.8 V Output Low Voltage 2.5 V Output Low Voltage
Symbol
VOH1 VOH2 VOL1 VOL2
Test Conditions
IOH = -4 mA, VDDQ = 1.6 V IOH = -8 mA, VDDQ = 2.375 V IOL = 4 mA IOL = 8 mA
Min
VDDQ - 0.4 V 1.7 V -- --
Max
-- -- 0.4 V 0.4 V
Rev: 1.02a 6/2006
12/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Operating Currents
-250 Parameter Test Conditions Mode Symbol 0 to 70C
350 75 265 50 40 40 85 60
-200 -40 to 85C
360 75 275 50 50 50 90 65
-150 -40 to 85C
300 55 240 45 50 50 90 55
0 to C
290 55 230 45 40 40 85 50
0 to 70C
230 40 210 40 40 40 85 50
-40 to 85C
240 40 220 40 50 50 90 55
Unit
Operating Current
Device Selected; All other inputs VIH or VIL Output open ZZ VDD - 0.2 V Device Deselected; All other inputs VIH or VIL
Pipeline (x72) Flow Through Pipeline Flow Through Pipeline -- Flow Through
IDD IDDQ IDD IDDQ ISB ISB IDD IDD
mA mA mA mA mA mA
Standby Current Deselect Current
--
Notes: 1. IDD and IDDQ apply to any combination of VDD and VDDQ operation. 2. All parameters listed are worst case scenario.
Rev: 1.02a 6/2006
13/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
AC Electrical Characteristics
Parameter
Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery
Symbol
tKC tKQ tKQX tLZ tS tH tKC tKQ tKQX tLZ tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR
1 1
-250
Min 4.0 -- 1.5 1.5 1.5 0.2 5.5 -- 2.0 2.0 1.5 0.5 1.3 1.7 1.5 -- 0 -- 5 1 20 Max -- 3.0 -- -- -- -- -- 5.5 -- -- -- -- -- -- 3.0 3.0 -- 3.0 -- -- -- Min 5.0 -- 1.5 1.5 1.5 0.4 6.5 -- -- 2.0 1.5 0.5 1.3 1.7 1.5 -- 0 -- 5 1 20
-200
Max -- 3.0 -- -- -- -- -- 6.5 6.5 -- -- -- -- -- 3.0 3.0 -- 3.0 -- -- -- Min 6.7 -- 1.5 1.5 1.5 0.5 7.5 -- -- 2.0 1.5 0.5 1.5 1.7 1.5 -- 0 -- 5 1 20
-150
Max -- 3.8 -- -- -- -- -- 7.5 7.5 -- -- -- -- -- 3.0 3.8 -- 3.8 -- -- --
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Pipeline
Flow Through
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.02a 6/2006
14/29
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Pipeline Mode Timing (SCD)
Begin
Read A
Cont
Cont
Deselect Write B Single Write tKL tKH tKC
Read C
Read C+1 Read C+2 Read C+3 Cont Burst Read
Deselect
Single Read
CK ADSP tS tH ADSC tS ADV tS tH A0-An
A B C ADSC initiated read
tH
tS GW tS BW tH tS Ba-Bd tS tH E1 tS tH E2 tS tH E3 G tS tOE DQa-DQd tOHZ
Q(A) D(B) E2 and E3 only sampled with ADSP and ADSC E1 masks ADSP Deselected with E1
tH
tKQ tH tLZ
Q(C) Q(C+1) Q(C+2)
tKQX tHZ
Q(C+3)
Rev: 1.02a 6/2006
15/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Flow Through Mode Timing (SCD)
Begin
Read A
Cont tKL tKH
Cont tKC
Write B
Read C
Read C+1 Read C+2 Read C+3 Read C
Cont
Deselect
CK ADSP tS tH ADSC tS tH ADV tS tH A0-An
A B C Fixed High
tS tH ADSC initiated read
tS tH GW tS tH BW tS tH Ba-Bd tS tH E1 tS tH E2 tS tH E3 G tH tS tOE DQa-DQd
Q(A) Deselected with E1
E2 and E3 only sampled with ADSC
tOHZ
D(B)
tKQ tLZ
Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tHZ tKQX
Rev: 1.02a 6/2006
16/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Pipeline Mode Timing (DCD)
Begin
Read A
Cont
Deselect Deselect Write B tKL tKH tKC
Read C
Read C+1 Read C+2 Read C+3 Cont
Deselect Deselect
CK ADSP tS tH ADSC tS ADV tS tH Ao-An
A B C ADSC initiated read
tH
tS GW tS BW tH tS Ba-Bd tS tH E1 tS tH E2 tS tH E3 G tS tOE DQa-DQd
Hi-Z E2 and E3 only sampled with ADSC Deselected with E1
tH
tKQ tH tLZ
Q(C) Q(C+1) Q(C+2) Q(C+3)
tHZ tKQX
tOHZ
Q(A) D(B)
Rev: 1.02a 6/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Flow Through Mode Timing (DCD)
Begin
Read A
Cont tKL tKH
Deselect Write B tKC
Read C
Read C+1 Read C+2 Read C+3 Read C
Deselect
CK ADSP tS tH ADSC tH tS ADV tS tH Ao-An
A B C Fixed High
tS tH ADSC initiated read
tS
tH
tS tH GW tS tH BW tH tS Ba-Bd tS tH E1 tS tH E2 tS tH E3 G tOE tKQ DQa-DQd
Q(A) E1 masks ADSP Deselected with E1
E2 and E3 only sampled with ADSP and ADSC
E1 masks ADSP
tH tS tOHZ
D(B)
tLZ
Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
tKQX tHZ
Rev: 1.02a 6/2006
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing
tKH tKC CK Setup Hold ADSP ADSC tZZR tZZS ZZ tZZH tKL
Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.02a 6/2006
19/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.02a 6/2006
20/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
* * *
108
*
*
*
*
*
*
* *
1
Boundary Scan Register
0
Bypass Register
210
0
Instruction Register TDI ID Code Register
31 30 29
TDO
*
***
210
Control Signals TMS TCK Test Access Port (TAP) Controller
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.02a 6/2006
21/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
ID Register Contents
GSI Technology JEDEC Vendor ID Code Presence Register 0 1
Not Used
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X X X X X X X X X X X X X 0 0 011011001
Tap Controller Instruction Set
Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
Rev: 1.02a 6/2006
22/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0
Update IR
1 0
Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins.
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(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary Instruction
EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU
Code
000 001 010 011 100 101 110
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1 1 1 1 1 1
BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.02a 6/2006
24/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version) Parameter
1.8 V Test Port Input Low Voltage 2.5 V Test Port Input Low Voltage 1.8 V Test Port Input High Voltage 2.5 V Test Port Input High Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low
Symbol
VILJ1 VILJ2 VIHJ1 VIHJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
-0.3 -0.3 0.6 * VDD1 0.6 * VDD2 -300 -1 -1 1.7 -- VDDQ - 100 mV --
Max.
0.3 * VDD1 0.3 * VDD2 VDD1 +0.3 VDD2 +0.3 1 100 1 -- 0.4 -- 100 mV
Unit Notes
V V V V uA uA uA V V V V 1 1 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9
Notes: 1. Input Under/overshoot voltage must be -2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOLJC = +100 uA
JTAG Port AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
VDD - 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ
JTAG Port AC Test Load
50 VDDQ/2
* Distributed Test Jig Capacitance
30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted.
Rev: 1.02a 6/2006
25/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
JTAG Port Timing Diagram
tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input
tTKH
tTKL
JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 -- 20 20 10 10 Max -- 20 -- -- -- -- Unit ns ns ns ns ns ns
Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com.
Rev: 1.02a 6/2006
26/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
C A1 A aaa D D1
Side View
e
Bottom View
E1 b e
Symbol A A1 b c D Rev 1.0
Min -- 0.40 0.50 0.31 21.9
Typ -- 0.50 0.60 0.36 22.0
Max 1.70 0.60 0.70 0.38 22.1
Units mm mm mm mm mm
Symbol D1 E E1 e aaa
Min -- 13.9 -- -- --
Typ 18.0 (BSC) 14.0 10.0 (BSC) 1.00 (BSC) 0.15
E
Max -- 14.1 -- -- --
Units mm mm mm mm mm
Rev: 1.02a 6/2006
27/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
Ordering Information for GSI Synchronous Burst RAMs Org
256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72 256K x 72
Part Number1
GS816272CC-250V GS816272CC-200V GS816272CC-150V GS816272CC-250IV GS816272CC-200IV GS816272CC-150IV GS816272CGC-250V GS816272CGC-200V GS816272CGC-150V GS816272CGC-250IV GS816272CGC-200IV GS816272CGC-150IV
Type
SCD/DCD SCD/DCD SCD/DCD SCD/DCD SCD/DCD SCD/DCD SCD/DCD SCD/DCD SCD/DCD SCD/DCD SCD/DCD SCD/DCD
Voltage Option
1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V
Package
209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA RoHS-compliant 209 BGA RoHS-compliant 209 BGA RoHS-compliant 209 BGA RoHS-compliant 209 BGA RoHS-compliant 209 BGA RoHS-compliant 209 BGA
Speed2 (MHz/ns)
250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5 250/5.5 200/6.5 150/7.5
TA3
C C C I I I C C C I I I
Status4
MP MP MP MP MP MP PQ PQ PQ PQ PQ PQ
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816236CC-250IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. MP = Mass Production. PQ = Pre-Qualification. 5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 1.02a 6/2006
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(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS816272CC-xxxV
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old; New 8162VxxC_r1 8162VxxC_r1; 8162VxxC_r1_01 8162VxxC_r1; 8162xxC_V_r1_02 Content Types of Changes Format or Content Page;Revisions;Reason * Creation of new datasheet * Added 200 & 150 MHz speed bins * Corrected block diagram (added references to E2 & E3) * Corrected truth table (addded references to E2 & E3) * Added Pb-free information * Changed part numbering due to nomenclature change * (Rev1.02a: Corrected JTAG Op Cond table)
Content
Rev: 1.02a 6/2006
29/29
(c) 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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